• 采用 3 个 74LS138 模块、和基本逻辑门电路实现 5 输入多数表决器

dec_74LS138（3-8 译码器）

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/04/08 10:25:45
// Design Name: 
// Module Name: dec_74LS138
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module dec_74LS138(
   input logic G,G2A,G2B,
   input logic [2:0] D,
   output logic [7:0] Y
    );
    always_comb begin
    if(G==0)  Y=8'b11111111;
    else if(G2A==1)  Y=8'b11111111;
    else if(G2B==1)  Y=8'b11111111;
    else begin
    case(D)
    3'b000: Y=8'b11111110;
    3'b001: Y=8'b11111101;
    3'b010: Y=8'b11111011;
    3'b011: Y=8'b11110111;
    3'b100: Y=8'b11101111;
    3'b101: Y=8'b11011111;
    3'b110: Y=8'b10111111;
    3'b111: Y=8'b01111111;
    endcase
    end
    end
endmodule

v1.sv（结构化建模）

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/04/08 10:26:54
// Design Name: 
// Module Name: voter5
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module v1(
   input logic [4:0] I,
   output  logic pass

    );
    logic G=1'b1;
    logic G1=1'b0;
    logic G2=1'b0;
    logic [7:0] Y5;
    logic [7:0] Y6;
    logic [7:0] Y7;
    logic  A1,A2,A3;
    dec_74LS138 T5 (.G(G),.G2A(G1),.G2B(I[3]),.D(I[2:0]),.Y(Y5));
    dec_74LS138 T6 (.G(G),.G2A(I[4]),.G2B(G2),.D(I[2:0]),.Y(Y6));
    dec_74LS138 T7 (.G(G),.G2A(G1),.G2B(G2),.D(I[2:0]),.Y(Y7));
    assign A1= (!((~Y5)|(~Y6)))&(Y7[0]);
    assign A2= Y5==8'b11111111 ?  (Y7[0]& Y7[1]& Y7[2]& Y7[4]) :(!Y7[7]);
    assign A3= Y6==8'b11111111 ?  (Y7[0]& Y7[1]& Y7[2]& Y7[4]) :(!Y7[7]);
    assign pass=A1|A2|A3;
  
endmodule

v1_tb.sv(测试文件)

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/04/07 19:41:43
// Design Name: 
// Module Name: voter5_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module  vi_tb();
 logic [4:0] I;
 logic  pass;
 integer i;
 v1 DUT(.I(I),.pass(pass));
 initial begin
   for(i=0;i<32;i=i+1) begin
    I=i;
    #20;   
    end
 end
 initial begin
 $timeformat(-9,0,"ns",5);
 $monitor("At time %t: I=%b,pass=%b",$time,I,pass);
 end
endmodule

v1.xdc(约束文件)

set_property -dict {
    PACKAGE_PIN B9  IOSTANDARD LVCMOS33} [get_ports {
    I[0]}];
set_property -dict {
    PACKAGE_PIN D11  IOSTANDARD LVCMOS33} [get_ports {
    I[1]}];
set_property -dict {
    PACKAGE_PIN B11  IOSTANDARD LVCMOS33} [get_ports {
    I[2]}];
set_property -dict {
    PACKAGE_PIN B12  IOSTANDARD LVCMOS33} [get_ports {
    I[3]}];
set_property -dict {
    PACKAGE_PIN A10  IOSTANDARD LVCMOS33} [get_ports {
    I[4]}];

set_property -dict {
    PACKAGE_PIN K13  IOSTANDARD LVCMOS33} [get_ports {
    pass}];